1. Field of the Invention
The present invention relates to reducing the noise generated by integrated circuit output buffers during switching.
2. Description of the Prior Art
An integrated circuit (IC) typically communicates to external devices through electrical conductors driven by output buffers. A buffer is a circuit designed to provide adequate current drive capability to charge up the capacitive load presented by the external conductors at a sufficiently fast rate to allow signals to be sent at the desired speed. The speed at which a buffer can raise a voltage from a low logic level (e.g., near 0 volts) to a high logic level (e.g., near 5 volts) is referred to as the "rise time". Similarly, the speed at which the buffer can reduce the voltage from high to low levels is the "fall time". With CMOS integrated circuits, the speed of data communications to external devices presently ranges up to several tens of million bits per second, with increases to over one hundred million bits per second likely in the near future. Therefore, the rise and fall times are typically required to be less than about 10 nanoseconds at present, with significant reductions required for the future.
One problem associated with signals having rapid rise and fall times is the electrical noise they produce in others parts of the integrated circuit. That is, stray capacitance and inductance cause some of the signal energy to couple to other portions of the integrated circuit, or to other conductors external to the IC. In addition, inductance in the ground path causes voltage spikes to appear due to rapid current variations caused by the output buffers. These problems generally become more severe as the rise and fall times become shorter. In most cases, integrated circuit output buffers are designed so that the rise and fall times are sufficiently fast to drive the load under worst case conditions. For CMOS integrated circuits, the worst case conditions are slower than nominal process speeds, low power supply voltages (e.g., about 4.75 volts for a nominal 5 volt supply), and high operating temperatures. However, under the best case conditions, the rise and fall times may then be so short as to generated excessive noise. The "process speed" refers to the fact that due to the tolerances for a given IC production process, some IC's turn out to be "fast", and others "slow", as compared to IC's produced by an average or nominal process. That is, a given production run may produce devices that switch signals more quickly than average, being referred to as a "fast" process, and vice-versa for a "slow" process. Hence, an output buffer design that satisfies the speed requirements may violate the noise requirements, and vice-versa.
It is desirable to have an integrated circuit that generates low noise while having the ability to communicate at a sufficiently high data rate over conductors presenting a significant capacitive load.